Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
The present invention relates to memory devices; more particularly, the present invention relates to static random access memories (SRAMs).
Since the dawn of the electronic revolution in the 1970""s, continuous technological advances in the computer industry have depended upon the ability to store and retrieve an ever-increasing amount of data quickly and inexpensively. Thus, the development of the semiconductor memory has played a major role in the advancement of the computer industry over the past few decades.
In particular, with the growing demand for large-scale on-chip cache memory for high performance microprocessors, a high-density static random access memories (SRAM) design becomes more significant. Traditionally six transistor (6T) SRAM cells have been implemented for cache memory devices. However, the size of 6T SRAM cells have become undesirable. As a result, four transistor (4T) SRAM cells have become more desirable because of smaller cell areas. Nonetheless, there is a problem with the design of 4T SRAM cells since it is typically difficult to meet read stability requirements.